1. Field of the Invention
The present invention relates in general to communication receivers and in particular to a system for providing economical automatic gain control for a communication receiver.
2. Description of Related Art
The IEEE 802.3ab (“Ethernet”) standard defines a digital media interface commonly used for transmitting data between computers linked through a network. The standard includes a “1000BASE-T” protocol enabling transceivers to communicate with one another through pulse amplitude modulation (PAM) signals conveyed on a set of four category 5 (CAT5) unshielded twisted-pair (UTP) conductors. A transceiver operating in accordance with the 1000BASE-T protocol can transmit and receive one 8-bit word every 8 nsec, thereby providing an effective communication rate of one gigabit per second in both directions.
Since each bit combination of a data word to be transmitted via a 1000BASE-T system may be treated as a symbol, for example representing a number or letter, an 8-bit word can be any of 256 different symbols. A 1000BASE-T transmitter maps the 256 symbols of each word into a separate combination of voltage levels of the set of four PAM signals, and it can change the PAM signal voltage level every 8 ns. The 1000BASE-T standard specifies a PAM-5 encoding scheme in which each of the four UTP conductors is allocated one of 5 symbols for each word to be transmitted, so that the four PAM signals can collectively represent 54 (625) different symbols. The data sequences to be transmitted are encoded in a manner that maps the 256 8-bit data symbols into 512 of the 625 available PAM-5 symbols. The remaining 113 PAM-5 symbols are available for use as control codes.
As the 1000BASE-T signal passes from a transmitter to a receiver, it can be distorted in ways that can make it difficult for the receiver to extract the data conveyed by the waveform. When the signal has relatively few transitions during a relatively long period, it acts as a low frequency signal. Magnetic coupling modules that link the UTP cables to the transceivers act like high pass filters which attenuate low frequency signal components, thereby causing a type of distortion known as “baseline wander”. “Insertion loss” is signal distortion due to attenuation caused by the impedance of the UTP cable conveying the 1000BASE-T signals between transceivers. A 1000BASE-T transceiver can transmit and receive signals at the same time over the same twisted pair, and the echo of a transceiver's outgoing signal distorts its incoming signal. A 1000BASE-T transceiver includes a separate channel for each of the four UTPs through which it communicates and an incoming signal arriving on any one UTP will include some “near end crosstalk” (NEXT) noise caused by the outgoing signals transmitted on the other UTPs. Since the four twisted pair are bundled into the same cable and are unshielded, an incoming 1000BASE-T signal arriving on any one of the four UTPs will included some “far end crosstalk” (FEXT) distortion caused by the 1000BASE-T signals arriving on the other three UTPs. Since the four UTPs may have slightly different number of twists per unit length, the actual lengths of the four UTPs within the same cable may differ, and therefore the four UTPs may provide differing signal path delays. Thus the four signals passing over the four UTPs can have a timing mismatch when they arrive at a receiver. 1000BASE-T receivers therefore include circuits for compensating incoming 1000BASE-T signal for these various types of distortion before that they can detect the data sequences represented by those signals.
Typical Prior Art Transceiver Circuit
FIG. 1 illustrates a prior art 1000BASE-T transceiver 10 in block diagram form. Transceiver 10 includes a transmit physical coding sublayer (PCS) 12 for scrambling and encoding an incoming sequence of 8-bit words Tx to produce four sequences of 3-bit data words Tx, a-Tx, d, each of which is an integer value of the set {−2, −1, 0, +1 or +2} and referencing one of the five PMA-5 symbols. Each data word Tx, a-Tx, d is supplied as input to a separate one of a set of four “physical medium attachment” (PMA) units 16(A)–16(D), and each PMA unit 16(A)–16(D) sets the voltage of a differential 1000BASE-T signal it transmits on a corresponding one of four UTPs A–D to one of the five voltage levels referenced by its input data Tx, a-Tx, d. Each PMA unit 16(A)–16(D) also detects the data sequence conveyed by an incoming 1000BASE-T signal transmitted by a remote transceiver on its corresponding UTP A-D and supplies that data sequence Rx, a-Rx, d to receive PCS 14. Receive PCS 14 de-scrambles and decodes the four Rx, a-Rx, d data sequences from PMAs 16(A)–16(D) to produce a single 8-bit output data word sequence Rx matching the remote transceiver's 8-bit input data sequence.
FIG. 2 illustrates PMA 16(A) of FIG. 1 in more detailed block diagram form; PMAs 16(B)–16(D) of FIG. 1 are similar. PMA 16(A) includes a transmitter 18 for sending a 1000BASE-T signal outward on UTP A in response to the incoming 3-bit Tx, a data sequence, a receiver 20 for generating the 3-bit output data sequence Rx, a in response to an incoming 1000BASE-T signal arriving on UTP A, and a “hybrid” circuit 22 for coupling the transmitter and receiver to UTP A.
Transmitter 18 includes a digital partial response (PR) filter 24 for converting the incoming Tx, a data sequence into a “partial response” data sequence indicating the voltage of each successive level of the outgoing 1000BASE-T signal. A digital-to-analog converter (DAC) 26 converts each word of the partial response sequence output of filter 24 into the indicated one of five 1000BASE-T analog voltage levels. A low pass filter (LPF) 27 filters any high frequency noise out of the DAC output signal, and a driver 28 responds to the output of LPF 27 by transmitting the 1000BASE-T signal outward on UTP A via hybrid 22.
Hybrid 22 passes the incoming 1000BASE-T signal P1 representing a sequence of first data elements D1 from a remote transceiver arriving on UTP A to receiver 20. Receiver 20 includes an amplifier 32 for amplifying the incoming 1000BASE-T signal with an adjustable gain (G1) and offset (OFF1). A low pass filter 34 removes high frequency noise from the amplifier output signal to produce an analog signal P2. An analog-to-digital converter (ADC) 36 digitizes the P2 signal to produce a sequence of second data elements D2 representing successive magnitudes of the P2 signal.
An automatic gain control (AGC) circuit 54 controls the gain G1 of amplifier 32 to compensate for insertion loss and to make sure that the peak-to-peak amplitude of the analog signal P2 supplied as input to ADC 36 remains close to the ADC's full input range. The transmit PCS 12 (FIG. 1) of a 1000BASE-T transmitter scrambles and encodes the Tx, a-Tx, d sequences in such a way as to ensure that over time the 1000BASE-T signals conveyed on UTPs A–D will have a constant, predictable root mean square (RMS) value. AGC circuit 54 monitors the D2 sequence output of ADC 36 and adjusts amplifier gain G1 to ensure that the average RMS value of the input signal to ADC 36 remains close to a target RMS value, thereby ensuring that ADC 36 will operate over its full scale range. A baseline wander (BLW) correction circuit 50 controls the value of the OFF1 data controlling the offset of amplifier 32.
A feedforward equalizer (FFE) 38 decodes the sequence of second data elements D2 and compensates it for distortions introduced by the UTP. The amount of echo distortion of the incoming 1000BASE-T signal is proportional to the magnitude of the outgoing 1000BASE-T signal transmitter 18 is currently sending outward on UTP A. The amount of near end crosstalk (NEXT) distortion in the incoming 1000BASE-T signal is proportional to the magnitude of the outgoing 1000BASE-T signals being transmitted outward by transmitters within the other three PMAs 16(B)–16(D) of FIG. 1. An echo/NEXT canceller circuit 40 monitors the Tx, a-Tx, d signals produced by all four transmitters and supplies an offset data sequence OFF2 to a summer 42 representing the magnitude of echo and NEXT distortion that has been added to the incoming signal. Summer 42 subtracts the OFF2 sequence generated by echo/NEXT canceller 40 from the output data sequence produced by FFE 38 to produce a 5-level partial response data sequence that is compensated for echo and NEXT distortion.
A multiplier 44 and a summer 45 amplify and offset the output sequence of summer 42 by a gain G2 and an offset OFF3 to produce a sequence of 8-bit third data elements D3. Each third data sequence element D3 corresponds to a separate one of the first data sequence elements D1 represented by the incoming 1000BASE-T signal and has a real number value that is proportional to a product of the integer value of its corresponding data sequence element D1 and gain G2 when OFF3 is appropriately adjusted. Since each first data sequence element D1 has an integer value of the set {−2, −1, 0, +1, +2}, then when gain G2 and OFF3 are properly adjusted, each 8-bit third data sequence element D3 will be relatively close in magnitude to one of the integer values of the set {−2, −1, 0, +1, +2}. However if either gain G2 or OFF2 are too high or too low, then each third data D3 will have a real number value that is somewhat larger or smaller than the integer value of its corresponding first sequence element D1.
12A slicer 46 rounds off each 8-bit “soft decision” data sequence element D3 to produce a corresponding 3-bit “hard decision” data sequence element D4 representing the nearest integer value of the set {−2, −1, 0, +1, +2}. A decision feedback estimator (DFE) 47 processes the fourth data element sequence D4 to control the offset data OFF3 supplied to summer 45. DFE 47 is able to determine whether OFF2 is correctly adjusted by detecting whether values of elements of the slicer's “soft decision” D3 sequence input are consistently higher or lower than the integer values {−2, −1, 0, +1, +2} of corresponding fourth data sequence elements D4 of the slicer's “hard decision” output sequence. When gain G2 is adequately adjusted, squares of the values of corresponding third and fourth data sequence elements D3 and D4 will be very close in value. The average (mean) difference between the squares of corresponding third and fourth data sequence elements D3 and D4 indicates a direction in which gain G2 should be adjusted. AGC 56 therefore continuously computes the mean of the difference between squares of corresponding D3 and D4 data sequence elements and adjusts gain G2 accordingly to keep that mean as small as possible.
A timing control circuit 48 monitors the sequences of third and fourth data elements D3 and D4 to determine the phase of the incoming 1000BASE-T signal's 125 MHz data cycle and produces timing signals for clocking the various receiver 20 components that processes the incoming signal. BLW correction circuit 50 monitors the sequence of fourth data elements D4 to determine how to adjust the OFF1 data input to amplifier 32 to compensate for baseline wander. An adaptation circuit 52 processes the sequences of third and fourth data elements D3 and D4 to determine how to set filter coefficients within FFE 38, echo/NEXT canceller 40 and BLW correction circuit 50.
AGC 54 is called a “non-data-aided RMS AGC” because it is not concerned with the data content D1 conveyed by the incoming 1000BASE-T signal when adjusting the gain G1 of amplifier 32; it is only concerned with the RMS value of the D2 data sequence output of ADC. AGC 56 is called a “data-aided LMS” AGC because its decision as to whether to increase or decrease the gain G2 of multiplier 44 is based a least means square algorithm processing data values represented by corresponding third and fourth data sequence elements D3 and D4 which are alternative 8-bit and 3-bit representations of the first data sequence elements D1 conveyed by the incoming 1000BASE-T signal.
While the prior art receiver 20 architecture illustrated in FIG. 2 is well-adapted for extracting the data content of incoming 1000BASE-T signal P1, the conventional AGCs 54 and 56 are expensive. AGC 54 uses a digital multiplier when calculating the RMS amplitude of digital data sequence D2 to determine how to adjust gain G1, and AGC 56 uses two digital multipliers to calculate the squares of the third and fourth data sequence elements D3 and D4 when determining how to adjust gain G2. Since digital multipliers are expensive, what is needed is a receiver including inexpensive non-data-aided and data-aided AGC circuits that can accurately control gains G1 and G2 without having to use expensive multipliers.